SPL-G1 is a dedicated hardware causal-audit Trusted Compute Unit built for security scenarios — it is not a general-purpose CPU/GPU/NPU, but a primitive that delivers provable causal audit at the hardware level. Every operation produces an auditable, traceable P→Q causal pair; on a violation, the fuse locks permanently.
Built on a 2D PIM (processing-in-memory) array and the RA-BUS unified addressing bus, SPL-G1 fuses three-mode compute (SCALAR / VECTOR / MATRIX) with hardware-level causal-constraint checking, 256-bit identity anchoring, and an irreversible SBC fuse into a single unit.
SPL-G1 is a hardware causal-audit Trusted Compute Unit (TCU). A 4×4 PIM in-memory-compute grid forms its compute base; together with a sequencer, a causal-verification unit, an identity-anchor unit, and a fuse unit, it provides an embedded security root for compliance computing, safety-critical auditing, and remote attestation.
| ✅ It is | ❌ It is not |
|---|---|
| A hardware causal-audit Trusted Compute Unit (TCU) | A desktop CPU (running Linux / x86 apps) |
| A verifiable compute primitive with full-lifecycle P→Q provenance | A GPU with thousands of cores and a CUDA ecosystem |
| A three-mode PIM array (SCALAR / VECTOR / MATRIX) with per-operation audit | A datacenter-class NPU accelerator for LLM inference |
| An embedded security root for compliance, safety-critical audit, and remote attestation | A replacement for any mainstream microprocessor |
A parameterized 256-entry program memory with JMP / JZ / JNZ / CALL / RET / HALT control-flow instructions and an 8-level return stack, with bounds protection.
Sign / 5-bit exponent / 10-bit mantissa, with subnormal, NaN, ±Inf and roundTiesToEven; real FP16 ADD / SUB / MUL / CMP / MAC semantics.
Compiles a restricted C dialect (int variables, for / while / if-else, arithmetic, comparison) into SPL-G1 microcode CONFIG words, with a built-in --verify interpreter mode.
A 4-target address-decode bus (PIM / Audit / Identity / External) supporting READ / WRITE / EXECUTE / CONFIG transaction types.
spl_cim_causal_unit v2 hard-constraint checking: a constraint_bits == 64'hFF…FF identity test plus a 56-bit dep_mask dependency check with cascade failure; bridge mode passes all.
Audit failure → fuse_blown latched → outputs forced to zero; only a hardware reset can recover (Materica #4).
The TCU core loop is delivered end-to-end and verified by RTL simulation — the integrated testbench tb_G1_Integrated.sv (v3) passes the full Phase-A suite with 0 errors (Icarus Verilog).
# Clone (this repository is the Gitee mirror) git clone https://gitee.com/nohn-ecosystem/SPL-G1-general-purpose-processor.git cd SPL-G1 # Core EDA toolchain — pure Python ≥3.8, standard library only make demo-causal # EDA → RTL pipeline: causal design → PDK mapping → Verilog config python eda_cli.py --desc examples/causal_chain_demo.json \ --pdk pdk/silicon_cim_v1.json --strategy min_delay \ --output outputs/netlist.json --rtl --rtl-dir outputs/rtlgen/ # RTL simulation (requires Icarus Verilog 12.0+) make sim # build and run the full Phase-A suite, 0 errors make wave # open waveforms in GTKWave # Compile a C-subset program and verify its semantics python splcc.py tests/loop_sub.c --verify
The EDA toolchain covers parse → map → build → export → RTL generation (eda_parser / eda_mapper / eda_exporter / eda_rtlgen / EDA_fixed). PDK includes silicon_cim_v1.json (28nm CIM) and optical_mzi_photonics_v1.json (photonic). Language split: SystemVerilog 53.1% · Python 43.4%.
Free for personal, non-commercial research; government / enterprise commercial use requires a paid commercial license. PCT patent filed.
| Audience | Terms |
|---|---|
| Personal researchers | Free for non-commercial research, not for any commercial use |
| Government / enterprise | Prior written authorization required |
| How to apply | Global: ai@nohnlins.com · China: lin@secondai.top |
SPL-G1 是一枚面向安全场景的专用硬件因果审计可信计算单元 —— 它不是通用 CPU/GPU/NPU，而是一个在硬件层面提供可证明因果审计的原语。每次运算都产生一条可审计、可溯源的 P→Q 因果对；一旦违规，熔断即永久锁定。
基于 2D PIM（存内计算）阵列与 RA-BUS 统一寻址总线，将三模计算能力（SCALAR / VECTOR / MATRIX）与硬件级因果约束校验、256 位身份锚定、不可逆 SBC 熔断机制结合于一体。
SPL-G1 是 硬件因果审计可信计算单元（TCU）。它以 4×4 PIM 存内计算网格为算力底座，配合顺序器、因果校验单元、身份锚定与熔断单元，为合规计算、安全关键审计与远程证明（attestation）场景提供嵌入式安全根。
| ✅ 是 | ❌ 不是 |
|---|---|
| 硬件因果审计可信计算单元（TCU） | 桌面级 CPU（运行 Linux / x86 应用） |
| 具备全生命周期 P→Q 溯源的可验证计算原语 | 拥有数千核心与 CUDA 生态的 GPU 显卡 |
| 三模 PIM 阵列（SCALAR / VECTOR / MATRIX），逐操作审计 | 面向 LLM 推理的数据中心级 NPU 加速器 |
| 合规计算、安全关键审计、远程证明工作负载的嵌入式安全根 | 任何主流微处理器的替代品 |
参数化 256 条程序存储，支持 JMP / JZ / JNZ / CALL / RET / HALT 控制流指令与 8 级返回栈，带越界保护。
符号 / 5 位指数 / 10 位尾数，支持次正规数、NaN、±Inf 与 roundTiesToEven；实现真正的 FP16 ADD / SUB / MUL / CMP / MAC 语义。
将受限 C 方言（int 变量、for / while / if-else、算术、比较）编译为 SPL-G1 微码 CONFIG 字，内置 --verify 解释器模式。
4 目标地址译码总线（PIM / Audit / Identity / External），支持 READ / WRITE / EXECUTE / CONFIG 事务类型。
spl_cim_causal_unit v2 硬约束校验：constraint_bits == 64'hFF…FF 恒等判定 + 56 位 dep_mask 依赖校验与级联失败；桥接模式全部通过。
审计失败 → fuse_blown 锁存 → 输出强制归零；仅硬件复位可恢复（Materica #4）。
TCU 核心环路端到端交付，并通过 RTL 仿真验证 —— 集成测试平台 tb_G1_Integrated.sv（v3）通过 Phase-A 全量测试套件，0 错误（Icarus Verilog）。
# 克隆（本仓库为 Gitee 镜像） git clone https://gitee.com/nohn-ecosystem/SPL-G1-general-purpose-processor.git cd SPL-G1 # 核心 EDA 工具链 —— 纯 Python ≥3.8，仅标准库 make demo-causal # EDA → RTL 流水线：因果设计 → PDK 映射 → Verilog 配置 python eda_cli.py --desc examples/causal_chain_demo.json \ --pdk pdk/silicon_cim_v1.json --strategy min_delay \ --output outputs/netlist.json --rtl --rtl-dir outputs/rtlgen/ # RTL 仿真（需 Icarus Verilog 12.0+） make sim # 构建并运行 Phase-A 全量套件，0 错误 make wave # 在 GTKWave 中打开波形 # 编译一个 C 子集程序并验证其语义 python splcc.py tests/loop_sub.c --verify
EDA 工具链覆盖 parse → map → build → export → RTL 生成（eda_parser / eda_mapper / eda_exporter / eda_rtlgen / EDA_fixed）。PDK 含 silicon_cim_v1.json（28nm CIM）与 optical_mzi_photonics_v1.json（光子）。语言分布：SystemVerilog 53.1% · Python 43.4%。
个人非商业研究免费；政府 / 企业商业使用需付费商业授权。PCT 专利已申请。
| 对象 | 条款 |
|---|---|
| 个人研究者 | 非商业研究免费，不得用于任何商业用途 |
| 政府 / 企业 | 需事先书面授权 |
| 申请方式 | 国际：ai@nohnlins.com · 中国：lin@secondai.top |